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(R)
Integrated Device Technology, Inc.
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
IDT74FCT163601/A ADVANCE INFORMATION
FEATURES:
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP * Extended commercial range of -40C to +85C * VCC = 3.3V 0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range * CMOS power levels (0.4W typ. static) * Rail-to-Rail output swing for increased noise margin * Low Ground Bounce (0.3V typ.) * Inputs (except I/O) can be driven by 3.3V or 5V components
DESCRIPTION:
The FCT163601/A 18-bit registered transceiver is built using advanced dual metal CMOS technology. These 18-bit
universal bus transceivers combine D-type latches and Dtype flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-toB data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. The FCT163601 has series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB CLKENAB CLKAB LEAB LEBA CLKBA CLKENBA OEBA
1 56 55 2 28 30
29 27
A1
3
CE 1D C1 CLK CE 1D C1 CLK
54
B1
TO 17 OTHER CHANNELS
3251 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
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DSC-3251/1
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IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 SO56-1 43 SO56-2 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0 pF
3251 lnk 04
NOTE: 1. This parameter is measured at characterization but not tested.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) VTERM(4) TSTG Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max. -0.5 to +4.6 -0.5 to +7.0 -0.5 to VCC + 0.5 -65 to +150 -60 to +60 Unit V V V C mA
B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA
IOUT
3251 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals.
FUNCTION TABLE(1,4)
CLKENAB
X X X H L L
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OEAB
H L L L L L L L
Inputs LEAB X H H L L L L L
CLKAB X X X X L H
A X L H X L H X X
Outputs B Z L H B0(2) L H B0(2) B0(3)
SSOP TSSOP/TVSOP TOP VIEW
L L
PIN DESCRIPTION
Pin Names Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs A to B Clock Enable Input (Active LOW) B to A Clock Enable Input (Active LOW)
3251 tbl 01
OEAB OEBA
LEAB LEBA CLKAB CLKBA Ax Bx
NOTES: 3251 tbl 02 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA and CLKENBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-impedance = LOW-to-HIGH Transition
CLKENAB CLKENBA
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IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 2.7V to 3.6V
Symbol VIH VIL II H II L IOZH IOZL VIK IODH IODL VOH Parameter Input HIGH Level (Input pins) Input HIGH Level (I/O pins) Input LOW Level (Input and I/O pins) Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage VCC = Max. VCC = Max. VI = 5.5V VI = VCC VI = GND VI = GND VO = VCC VO = GND VCC = Min., IIN = -18mA VCC = 3.3V, VIN = VIH or VIL, VO = VCC = 3.3V, VIN = VIH or VIL, VO = VCC = Min. VIN = VIH or VIL VCC = 3.0V VIN = VIH or VIL VCC = Min. VIN = VIH or VIL 1.5V(3) 1.5V(3) -- -- -- -- -- -- -- -36 50 VCC-0.2 2.4 2.4 (5) -- -- -- -- -60 -- --
-- -- -- -- -- -- -0.7
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level
Min. 2.0 2.0 -0.5
Typ.(2) -- --
--
Max. 5.5 VCC+0.5 0.8 1 1 1 1 1 1
-1.2
Unit V V A
A V mA mA V
-60 90 -- 3.0 3.0 -- 0.2 0.3 0.3
-135
-110 200 -- -- -- 0.2 0.4 0.55 0.50 -240
--
IOH = -0.1mA IOH = -3mA IOH = -8mA IOL = 0.1mA IOL = 16mA IOL = 24mA
VOL
Output LOW Voltage
V
IOS VH ICCL ICCH ICCZ
Short Circuit Current(4) Input Hysteresis Quiescent Power Supply Current
VCC = 3.0V IOL = 24mA VIN = VIH or VIL VCC = Max., VO = GND(3)
--
mA mV A
150 0.1
VCC = Max., VIN = GND or VCC
10
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC -0.6V at rated current.
3251 lnk 05
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IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = VCC -0.6V(3 Min. -- VIN = VCC VIN = GND -- Typ.(2) 2.0 60 Max. 30 100 Unit A A/ MHz
OEAB = VCC OEBA = GND
One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC OEBA = GND LEBA = GND CLKENBA = GND One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC OEBA = GND LEBA = GND CLKENBA = GND Eighteen Bits Toggling fi = 2.5MHz 50% Duty Cycle
VCC = Max., Outputs Open
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
0.6
1.0
mA
VIN = VCC -0.6 VIN = GND
--
0.6
1.0
VIN = VCC VIN = GND
--
3.0
5.0(5)
VIN = VCC -0.6 VIN = GND
--
3.0
5.3(5)
NOTES: 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
3251 tbl 06
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IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT163601 Symbol Parameter Condition(1) Min.(2) Max. Min.(2) FCT163601A Max. Unit
fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU
CLKAB or CLKBA
frequency(4)
CL = 50pF RL = 500
-- 1.5 1.5 1.5 1.5 1.5 4.0 0 2.5 2.0 3.0 1.5 0 3.0 3.0 --
100 6.5 7.2 7.3 7.5 6.5 -- -- -- -- -- -- -- -- -- 0.5
-- 1.5 1.5 1.5 1.5 1.5 3.0 0 2.5 2.0 2.5 1.0 0 2.5 3.0 --
150 5.5 6.2 6.3 6.5 5.2 -- -- -- -- -- -- -- -- -- 0.5
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3251 tbl 07
tSU tH tH tW
Propagation Delay Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA Hold Time HIGH or LOW Ax to CLKAB, Bx to CLKBA Set-up Time Clock HIGH or LOW LOW Ax to LEAB, Clock Bx to LEBA HIGH Set-up Time, CLKEN to CLK Hold Time, HIGH or LOW Ax to LEAB, Bx to LEBA Hold Time, CKLEN after CLK
LEAB or LEBA Pulse Width HIGH(4) tW CLKAB or CLKBA Pulse Width HIGH or LOW(4) tSK(o) Output Skew (3)
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This parameter is guaranteed but not tested.
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IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
6V V
CC
SWITCH POSITION
Open GND
500 V Pulse Generator R
T IN
V D.U.T.
OUT
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests
Switch 6V
50pF C
L
500
SET-UP, HOLD AND RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
tREM
tSU
tH
PROPAGATION DELAY
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
3251 lnk 07
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
GND Open
3251 tbl 08 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
3251 lnk 04
PULSE WIDTH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
3251 lnk 05
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
1.5V
3251 lnk 06
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY SWITCH 6V LOW tPZH OUTPUT NORMALLY HIGH SWITCH GND 3V 1.5V tPHZ 0.3V 1.5V 0V 0V
3251 lnk 08
DISABLE 3V 1.5V tPLZ 0V 3V 0.3V VOL VOH
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 3. If VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
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IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX FCT XXXX Temp. Range Device Type X Package
PV PA PF 163601 163601A 74
Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) Non-Inverting 18-Bit Registered Transceiver
-40C to +85C
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